A PLL synthesizer (U.S. Pat. No. 7,701,299) that achieves fast tuning speed and low phase-noise was recently introduced. This synthesizer has an initial tuning mechanism that uses a conventional divider loop to lock a voltage-controlled oscillator (VCO) to a desired output frequency. Once initial lock is achieved, the divider loop is switched out of the circuit in favor of a low phase-noise mixer loop.
The mixer loop provides a low phase-noise feedback path in the PLL. It produces a rich spectrum of regularly spaced frequencies and the PLL can potentially lock to any one of them. Normally, when the synthesizer switches from the divider loop to the mixer loop, the PLL output frequency does not change. This stability is obtained in part because the frequencies in the mixer loop are integer multiples of the phase detector comparison signal frequency. The integer division ratio in the divider branch may therefore be chosen to exactly match a multiplication coefficient in the mixer branch.
It is possible, however, that unusual circumstances could lead the synthesizer PLL to lock to an incorrect frequency in the mixer loop. Temporary failures of the PLL loop low-pass filter or loss of bias, for example, might lead the synthesizer to lock to the wrong frequency.